Digital Electronics MCQ – 27 previous year questions with solutions

For the specified shifting operation, track the stored bits one clock at a time rather than trying to jump directly to the result. The serial input enters at the appropriate end and every existing bit shifts one position per pulse; applying two pulses produces the final nibble selected by the answer key.

A serial-in/parallel-out register accepts one incoming bit per clock. With the rightmost bit transmitted first, perform two serial shifts from the stated initial register contents; the answer follows from those two state transitions.

A 4-bit shift register loaded in parallel still shifts one bit position for each clock pulse once placed in shift mode. Under the convention used in the question, it shifts one position to the right per clock.

Asynchronous or ripple counters clock each stage from the previous stage, so propagation delays accumulate. Synchronous counters clock all flip-flops together and are therefore faster, but combinational decoding can still exhibit hazards/glitches depending on implementation. Key relation: Ripple delay roughly accumulates with number of stages.

Exam focus: Synchronous eliminates ripple-clock delay, not every possible logic hazard. Common trap: Synchronous does not mean glitch-proof.

An n-bit binary counter has 2ⁿ distinct states. If it starts at 0, the highest count is therefore 2ⁿ − 1, giving the range 0 to 2ⁿ − 1.

Cascaded counters divide the clock by the product of their moduli. Here the total division factor is 5×8×10 = 400, so 12 MHz / 400 = 30 kHz.

Flip-flops and latches store state. In the basic active-high SR form, S=R=1 is forbidden/invalid. Key relation: JK with J=K=1 → toggle.

Exam focus: Race-around is associated especially with level-triggered JK at long clock pulses. Common trap: Do not credit level triggering itself with eliminating race-around.

A register is a group of flip-flops used to store a multi-bit word. Shift-register configurations can move data serially or in parallel and are widely used for serial/parallel conversion and temporary storage. Key relation: An n-bit register typically uses n storage elements.

Exam focus: Storage/shift is the register's core job; arithmetic needs extra logic. Common trap: Do not treat a register itself as an adder.

In an asynchronous ripple counter, the transition must propagate through successive flip-flops. With four flip-flops each having 15 ns clock-to-Q delay, the worst-case settling time is 4×15 = 60 ns.

Sequential circuits combine logic with memory, so outputs/state depend on present inputs and previous state. Flip-flops and latches provide storage. Key relation: x[k+1]=F(x[k],u[k]); y[k]=G(x[k],u[k]).

Exam focus: Look for state/memory before classifying a circuit as sequential. Common trap: Do not equate 'sequential' with 'asynchronous'.

A UART is designed to interface parallel data used inside a digital system with asynchronous serial data used on an external communication link. It performs parallel-to-serial transmission and serial-to-parallel reception.

A decoder maps an n-bit code to one of up to 2^n output lines, commonly as a one-hot output. Decoders are used in memory/address selection and can implement minterm-based logic functions. Key relation: n inputs → up to 2^n decoded outputs.

Exam focus: Only the selected output is asserted in ideal one-hot decoding. Common trap: All decoder outputs are not active simultaneously.

A BCD digit represents decimal 0–9 using four binary bits (8421 code). Therefore a 1-of-10 BCD decoder needs 4 input lines and produces ten decoded output lines.

A half adder adds two single-bit inputs. Its Sum output is 1 only when A and B are different, which is exactly the XOR truth table; the Carry output is A·B.

A useful classification test is whether the same present input can produce different outputs because of history. Adders, multiplexers, decoders and encoders are combinational; counters, registers and finite-state machines are sequential. Key relation: Combinational: y(t)=f[x(t)]. Sequential: y(t)=f[x(t), state(t)], with state(t+1)=g[x(t),state(t)].

Exam focus: Ask one question: “Does previous state matter?” If no → combinational. Common trap: Treating “timing operation” as proof that a circuit is combinational.

A multiplexer routes one of many data inputs to a single output according to select inputs. By wiring data inputs to constants/variables appropriately, a multiplexer can implement Boolean functions. Key relation: N=2^m inputs for m select lines.

Exam focus: MUX is both a selector and a logic-function building block. Common trap: Do not claim a MUX cannot implement arbitrary Boolean functions.

Boolean algebra has operation-specific laws. AND and OR satisfy commutative and associative laws; XOR also satisfies commutative and associative laws, although it is not idempotent (A⊕A=0). Key relation: NAND universality: NOT A=A NAND A; AND from double NAND; OR via De Morgan. XOR associativity: A⊕B⊕C is independent of grouping.

Exam focus: Do not confuse XOR’s non-idempotent property with associativity. Common trap: Assuming XOR is non-associative because its output changes with parity.

Boolean algebra provides identities such as absorption, De Morgan’s laws and distributive rules that systematically reduce a logic expression and therefore the required gate count. Truth tables verify equivalence, but they are not the primary algebraic reduction method.

Boolean algebra uses exact identities for logic simplification. De Morgan transforms complemented sums/products, while absorption removes redundant terms; care is needed because A+A'B simplifies to A+B, not A. Key relation: (A+B)'=A'B'; A+AB=A; A+A'B=A+B.

Exam focus: Test a doubtful identity with a two-row truth assignment. Common trap: Absorption identities with a complemented term are easy to misremember.

A digital memory is specified by number of addressable words times bits per word. With n address lines, up to 2^n locations can be selected; the number of data lines sets the word width. Key relation: Capacity=(2^n words)×m bits/word.

Exam focus: Address lines choose locations; data lines carry word bits. Common trap: Do not confuse address width with data width.

Programmable logic devices realize logic functions through programmable interconnect arrays. A PLA provides programmable AND and OR planes for high flexibility, while a PAL traditionally has a programmable AND plane and fixed OR plane. Key relation: PLA: programmable AND + programmable OR; PAL: programmable AND + fixed OR.

Exam focus: Use PLA for flexibility; PAL for simpler/faster structures. Common trap: Do not swap PLA and PAL programmability.

SRAM stores each bit in a bistable latch/flip-flop-like cell and does not need refresh while powered, giving fast access at the cost of area. DRAM stores charge on a capacitor, requires periodic refresh, and achieves higher density and lower cost per bit but is generally slower than SRAM.

Exam focus: Fast/cache → SRAM; dense/main memory → DRAM. Common trap: DRAM is not faster or more expensive per bit than SRAM.

An ADC discretizes both amplitude and time. Bit depth controls amplitude resolution; sampling frequency controls temporal/spectral resolution and aliasing. Key relation: LSB ≈ VFS/2^n (or VFS/(2^n−1), depending convention); ideal quantization error ≈ ±0.5 LSB; sampling theorem requires fs > 2fmax for ideal band-limited reconstruction.

Exam focus: Bits → amplitude resolution. Sampling rate → aliasing/reconstruction. Common trap: Saying “more bits means resolution is 1/n”; it is approximately one part in 2^n.

A DAC converts a digital code into a proportional analog voltage or current. The R-2R ladder uses only two resistor values, making matching and fabrication easier than a wide binary-weighted resistor range. Key relation: Ideal unipolar DAC: V_o∝V_ref×(digital code/2^n).

Exam focus: R-2R needs only R and 2R. Common trap: Reference voltage directly affects full-scale output.

CMOS inputs draw extremely small steady-state current and offer large noise margins, giving high input impedance and high fan-out in many logic applications. Traditional TTL uses bipolar transistors and has higher static power than CMOS under comparable conditions. Key relation: Fan-out is limited by input loading and output drive; CMOS input current is very small.

Exam focus: CMOS usually wins on static power. Common trap: Do not assume bipolar TTL has lower static power than CMOS.

One logic output can drive many logic inputs when the driving gate has low output impedance and the receiving gates have high input impedance. This minimizes loading, so the output voltage remains within valid logic levels even when several inputs are connected.

Among the listed choices, checksum coding is the method intended to provide stronger error detection, including many multi-bit error patterns. A simple parity bit reliably detects an odd number of bit errors but can miss two-bit errors because parity may remain unchanged.