Combinational Circuits MCQ [Free PDF] – 5 Objective Questions with Answers

A decoder maps an n-bit code to one of up to 2^n output lines, commonly as a one-hot output. Decoders are used in memory/address selection and can implement minterm-based logic functions. Key relation: n inputs → up to 2^n decoded outputs.

Exam focus: Only the selected output is asserted in ideal one-hot decoding. Common trap: All decoder outputs are not active simultaneously.

A BCD digit represents decimal 0–9 using four binary bits (8421 code). Therefore a 1-of-10 BCD decoder needs 4 input lines and produces ten decoded output lines.

A half adder adds two single-bit inputs. Its Sum output is 1 only when A and B are different, which is exactly the XOR truth table; the Carry output is A·B.

A useful classification test is whether the same present input can produce different outputs because of history. Adders, multiplexers, decoders and encoders are combinational; counters, registers and finite-state machines are sequential. Key relation: Combinational: y(t)=f[x(t)]. Sequential: y(t)=f[x(t), state(t)], with state(t+1)=g[x(t),state(t)].

Exam focus: Ask one question: “Does previous state matter?” If no → combinational. Common trap: Treating “timing operation” as proof that a circuit is combinational.

A multiplexer routes one of many data inputs to a single output according to select inputs. By wiring data inputs to constants/variables appropriately, a multiplexer can implement Boolean functions. Key relation: N=2^m inputs for m select lines.

Exam focus: MUX is both a selector and a logic-function building block. Common trap: Do not claim a MUX cannot implement arbitrary Boolean functions.