Sequential Circuits MCQ [Free PDF] – 11 Objective Questions with Answers

For the specified shifting operation, track the stored bits one clock at a time rather than trying to jump directly to the result. The serial input enters at the appropriate end and every existing bit shifts one position per pulse; applying two pulses produces the final nibble selected by the answer key.

A serial-in/parallel-out register accepts one incoming bit per clock. With the rightmost bit transmitted first, perform two serial shifts from the stated initial register contents; the answer follows from those two state transitions.

A 4-bit shift register loaded in parallel still shifts one bit position for each clock pulse once placed in shift mode. Under the convention used in the question, it shifts one position to the right per clock.

Asynchronous or ripple counters clock each stage from the previous stage, so propagation delays accumulate. Synchronous counters clock all flip-flops together and are therefore faster, but combinational decoding can still exhibit hazards/glitches depending on implementation. Key relation: Ripple delay roughly accumulates with number of stages.

Exam focus: Synchronous eliminates ripple-clock delay, not every possible logic hazard. Common trap: Synchronous does not mean glitch-proof.

An n-bit binary counter has 2ⁿ distinct states. If it starts at 0, the highest count is therefore 2ⁿ − 1, giving the range 0 to 2ⁿ − 1.

Cascaded counters divide the clock by the product of their moduli. Here the total division factor is 5×8×10 = 400, so 12 MHz / 400 = 30 kHz.

Flip-flops and latches store state. In the basic active-high SR form, S=R=1 is forbidden/invalid. Key relation: JK with J=K=1 → toggle.

Exam focus: Race-around is associated especially with level-triggered JK at long clock pulses. Common trap: Do not credit level triggering itself with eliminating race-around.

A register is a group of flip-flops used to store a multi-bit word. Shift-register configurations can move data serially or in parallel and are widely used for serial/parallel conversion and temporary storage. Key relation: An n-bit register typically uses n storage elements.

Exam focus: Storage/shift is the register's core job; arithmetic needs extra logic. Common trap: Do not treat a register itself as an adder.

In an asynchronous ripple counter, the transition must propagate through successive flip-flops. With four flip-flops each having 15 ns clock-to-Q delay, the worst-case settling time is 4×15 = 60 ns.

Sequential circuits combine logic with memory, so outputs/state depend on present inputs and previous state. Flip-flops and latches provide storage. Key relation: x[k+1]=F(x[k],u[k]); y[k]=G(x[k],u[k]).

Exam focus: Look for state/memory before classifying a circuit as sequential. Common trap: Do not equate 'sequential' with 'asynchronous'.

A UART is designed to interface parallel data used inside a digital system with asynchronous serial data used on an external communication link. It performs parallel-to-serial transmission and serial-to-parallel reception.