Memories & PLDs MCQ [Free PDF] – 3 Objective Questions with Answers

A digital memory is specified by number of addressable words times bits per word. With n address lines, up to 2^n locations can be selected; the number of data lines sets the word width. Key relation: Capacity=(2^n words)×m bits/word.

Exam focus: Address lines choose locations; data lines carry word bits. Common trap: Do not confuse address width with data width.

Programmable logic devices realize logic functions through programmable interconnect arrays. A PLA provides programmable AND and OR planes for high flexibility, while a PAL traditionally has a programmable AND plane and fixed OR plane. Key relation: PLA: programmable AND + programmable OR; PAL: programmable AND + fixed OR.

Exam focus: Use PLA for flexibility; PAL for simpler/faster structures. Common trap: Do not swap PLA and PAL programmability.

SRAM stores each bit in a bistable latch/flip-flop-like cell and does not need refresh while powered, giving fast access at the cost of area. DRAM stores charge on a capacitor, requires periodic refresh, and achieves higher density and lower cost per bit but is generally slower than SRAM.

Exam focus: Fast/cache → SRAM; dense/main memory → DRAM. Common trap: DRAM is not faster or more expensive per bit than SRAM.