Microprocessors & Microcontrollers MCQ – 22 previous year questions with solutions

The classic 8051 is an 8-bit Harvard-style microcontroller with separate code and data spaces. The standard core has 4 KB on-chip program ROM and 128 bytes internal RAM, supports external memory, multiple interrupts and configurable interrupt priority. Key relation: Reset SP=07H; classic internal RAM=128 bytes; standard ROM=4 KB.

Exam focus: Remember 07H for stack pointer reset. Common trap: 00H is not the reset value of the 8051 stack pointer.

An n-bit ADC divides its input range into roughly 2^n quantization levels. Quantization error is inherent in finite resolution, while sampling frequency determines whether the signal can be reconstructed without aliasing. Key relation: LSB≈V_FS/2^n; ideal quantization error ≈±0.5 LSB.

Exam focus: More bits improve amplitude resolution; higher sample rate improves time/frequency representation. Common trap: Resolution is not simply 1/n and sampling rate is not irrelevant.

The classic 8051 is an 8-bit Harvard-style microcontroller with separate code and data spaces. The standard core has 4 KB on-chip program ROM and 128 bytes internal RAM, supports external memory, multiple interrupts and configurable interrupt priority. Key relation: Reset SP=07H; classic internal RAM=128 bytes; standard ROM=4 KB.

Exam focus: Remember 07H for stack pointer reset. Common trap: 00H is not the reset value of the 8051 stack pointer.

The classic 8051 is an 8-bit Harvard-style microcontroller with separate code and data spaces. On reset the stack pointer is 07H, so the first PUSH stores at 08H. Key relation: Reset SP=07H; classic internal RAM=128 bytes; standard ROM=4 KB.

Exam focus: Remember 07H for stack pointer reset. Common trap: 00H is not the reset value of the 8051 stack pointer.

The classic 8051 is an 8-bit Harvard-style microcontroller with separate code and data spaces. The standard core has 4 KB on-chip program ROM and 128 bytes internal RAM, supports external memory, multiple interrupts and configurable interrupt priority. Key relation: Reset SP=07H; classic internal RAM=128 bytes; standard ROM=4 KB.

Exam focus: Remember 07H for stack pointer reset. Common trap: 00H is not the reset value of the 8051 stack pointer.

The classic 8051 is an 8-bit Harvard-style microcontroller with separate code and data spaces. The standard core has 4 KB on-chip program ROM and 128 bytes internal RAM, supports external memory, multiple interrupts and configurable interrupt priority. Key relation: Reset SP=07H; classic internal RAM=128 bytes; standard ROM=4 KB.

Exam focus: Remember 07H for stack pointer reset. Common trap: 00H is not the reset value of the 8051 stack pointer.

The classic 8051 is an 8-bit Harvard-style microcontroller with separate code and data spaces. The standard core has 4 KB on-chip program ROM and 128 bytes internal RAM, supports external memory, multiple interrupts and configurable interrupt priority. Key relation: Reset SP=07H; classic internal RAM=128 bytes; standard ROM=4 KB.

Exam focus: Remember 07H for stack pointer reset. Common trap: 00H is not the reset value of the 8051 stack pointer.

The classic 8051 is an 8-bit Harvard-style microcontroller with separate code and data spaces. The standard core has 4 KB on-chip program ROM and 128 bytes internal RAM, supports external memory, multiple interrupts and configurable interrupt priority. Key relation: Reset SP=07H; classic internal RAM=128 bytes; standard ROM=4 KB.

Exam focus: Remember 07H for stack pointer reset. Common trap: 00H is not the reset value of the 8051 stack pointer.

The classic 8051 is an 8-bit Harvard-style microcontroller with separate code and data spaces. On reset the stack pointer is 07H, so the first PUSH stores at 08H. Key relation: Reset SP=07H; classic internal RAM=128 bytes; standard ROM=4 KB.

Exam focus: Remember 07H for stack pointer reset. Common trap: 00H is not the reset value of the 8051 stack pointer.

In Mode 2 (rate generator), after N counts the output produces a LOW pulse lasting exactly one input clock period, then automatically reloads and repeats. Thus the LOW interval is one clock cycle.

In I/O mode, the 8255 Programmable Peripheral Interface configures Ports A, B and C as programmable input/output ports according to the control word and selected Mode 0, 1 or 2 behavior.

The RESET input initializes the DMA controller by clearing command, request and temporary registers and resetting internal sequencing such as the first/last flip-flop. Therefore RESET is the required pin.

The 8259A interrupt-acknowledge sequence may require idle timing between INTA̅ cycles to satisfy PIC speed and cascade-address delays. Under the specified interface convention, three idle states Ti are allowed, matching the final key.

In strobed input operation, a LOW pulse on STB̅ tells the 8255 that valid peripheral data is present and causes the input port data to be loaded into the input latch. The corresponding buffer-full/status logic is then updated.

A bus transfer protected by the active-low LOCK̅ signal has highest priority because the processor is explicitly preventing other bus masters from taking control during an indivisible/critical bus operation.

Under the 80286 bus-timing convention used by the question, a valid HOLD request is recognized only after completion of the specified bus-cycle sequence with the processor state/reset condition shown in the correct option. The official final answer is the 34-clock, 80286 RESET condition.

A CPU can be viewed as datapath + control. The datapath contains registers and ALU; the control unit decides which operation occurs and when, including read/write control signals to memory and I/O. Key relation: Conceptual data path: Memory/I-O ↔ buses/registers → ALU → registers; control unit generates READ, WRITE, enable and timing signals.

Exam focus: ALU = compute; control unit = coordinate; registers = fast temporary storage. Common trap: Attributing every CPU action, including memory bus control, to the ALU.

A usable 8086 stack requires both SS (Stack Segment) and SP (Stack Pointer) to be initialized. SS identifies the stack segment base and SP gives the offset of the current top of stack.

JNZ tests the zero flag and branches when Z=0. The timing depends on whether the jump is taken; under the processor/timing convention intended by this question, when the 'zero condition' is satisfied the execution path takes four clock cycles, matching the final key.

DAA (Decimal Adjust Accumulator) is used after adding packed BCD numbers so the binary result in the accumulator is corrected to a valid BCD representation. Hence it is associated with BCD addition.

In the 8085, restart instruction RST n vectors to address 8×n. Therefore RST 5 vectors to 5×8=40 decimal = 28H.

An interrupt-driven software system is organized into a main program plus the interrupt service routines required for the subprocesses/peripherals. Since the listed items are constituent parts of the complete software structure, 'all of the mentioned' is correct.