Every 8086 & Advanced Processors question asked in GPSC DEE Electrical, GPSC AE Electrical — solve, check instantly, then read the formula and exam tip.
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View answer & solution
A bus transfer protected by the active-low LOCK̅ signal has highest priority because the processor is explicitly preventing other bus masters from taking control during an indivisible/critical bus operation.
View answer & solutionUnder the 80286 bus-timing convention used by the question, a valid HOLD request is recognized only after completion of the specified bus-cycle sequence with the processor state/reset condition shown in the correct option. The official final answer is the 34-clock, 80286 RESET condition.
View answer & solutionA CPU can be viewed as datapath + control. The datapath contains registers and ALU; the control unit decides which operation occurs and when, including read/write control signals to memory and I/O. Key relation: Conceptual data path: Memory/I-O ↔ buses/registers → ALU → registers; control unit generates READ, WRITE, enable and timing signals.
Exam focus: ALU = compute; control unit = coordinate; registers = fast temporary storage. Common trap: Attributing every CPU action, including memory bus control, to the ALU.
View answer & solutionA usable 8086 stack requires both SS (Stack Segment) and SP (Stack Pointer) to be initialized. SS identifies the stack segment base and SP gives the offset of the current top of stack.
