Peripheral Interfacing MCQ [Free PDF] – 5 Objective Questions with Answers

In Mode 2 (rate generator), after N counts the output produces a LOW pulse lasting exactly one input clock period, then automatically reloads and repeats. Thus the LOW interval is one clock cycle.

In I/O mode, the 8255 Programmable Peripheral Interface configures Ports A, B and C as programmable input/output ports according to the control word and selected Mode 0, 1 or 2 behavior.

The RESET input initializes the DMA controller by clearing command, request and temporary registers and resetting internal sequencing such as the first/last flip-flop. Therefore RESET is the required pin.

The 8259A interrupt-acknowledge sequence may require idle timing between INTA̅ cycles to satisfy PIC speed and cascade-address delays. Under the specified interface convention, three idle states Ti are allowed, matching the final key.

In strobed input operation, a LOW pulse on STB̅ tells the 8255 that valid peripheral data is present and causes the input port data to be loaded into the input latch. The corresponding buffer-full/status logic is then updated.