JNZ tests the zero flag and branches when Z=0. The timing depends on whether the jump is taken; under the processor/timing convention intended by this question, when the 'zero condition' is satisfied the execution path takes four clock cycles, matching the final key.
Formula / Key Relation
JNZ condition:
Z = 0 → jump taken
Z = 1 → no jump
Detailed Explanation
Concept & ReasoningConditional-branch timing must be read together with the exact processor architecture because 8085, 8086 and later x86 devices use different timing units and instruction encodings. The conceptual rule remains: JNZ means 'jump if not zero', so Z=1 means the branch condition is false; only the fall-through path executes. The official answer should be retained with that timing convention.How to Solve It in the ExamDecode the flag condition before recalling cycle counts.Important Exam PointDo not transfer timing numbers from one processor family to another.Related Revision PathThis question sits in the revision path Microprocessors and Interfacing → Microprocessor Instructions →…
Concept & Reasoning
Conditional-branch timing must be read together with the exact processor architecture because 8085, 8086 and later x86 devices use different timing units and instruction encodings. The conceptual rule remains: JNZ means 'jump if not zero', so Z=1 means the branch condition is false; only the fall-through path executes. The official answer should be retained with that timing convention.
How to Solve It in the Exam
Decode the flag condition before recalling cycle counts.
Important Exam Point
Do not transfer timing numbers from one processor family to another.
Related Revision Path
This question sits in the revision path Microprocessors and Interfacing → Microprocessor Instructions → Conditional Branching .
Quick Trick
Decode the flag condition before recalling cycle counts.
Common Mistake
Reading JNZ as 'jump if zero'.
Exam Tip
Do not transfer timing numbers from one processor family to another.
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