A 4-bit ripple counter consists of flip-flops, where each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________
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In an asynchronous ripple counter, the transition must propagate through successive flip-flops. With four flip-flops each having 15 ns clock-to-Q delay, the worst-case settling time is 4×15 = 60 ns.
Formula / Key Relation
ttotal = n·tpd
= 4 × 15 ns
= 60 ns
Detailed Explanation
Concept & Reasoning
Unlike a synchronous counter, a ripple counter does not switch every flip-flop from a common clock edge. One stage's output triggers the next, so delays accumulate. The 1111→0000 recycle can require the change to ripple through all four stages, giving the worst-case propagation delay.
How to Solve It in the Exam
Ripple counter worst-case delay = number of stages × delay per stage.
Important Exam Point
This cumulative delay limits the maximum reliable clock frequency.
Related Revision Path
This question sits in the revision path Digital Electronics → Sequential Logic → Ripple Counters .
Quick Trick
Ripple counter worst-case delay = number of stages × delay per stage.
Common Mistake
Using only one flip-flop's 15 ns delay as the counter settling time.
Exam Tip
This cumulative delay limits the maximum reliable clock frequency.
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